Obtaining physiological data is essential to helping monitor health. To monitor heart rhythm, electrodes are placed on the skin to gather these measurements, producing an electrocardiogram (ECG). The ECG is a recorded electrical signal resulting from a contraction of the heart muscles. It can detect deviation from a normal heartbeat and can be used to diagnose illnesses or to optimize a training load.

ECG Basics and Analog Front-End Requirements

The electrical signal must first be amplified to a level that is suitable for recording (electrodes on the arms can give voltages in the range of tens of microvolts to a millivolt peak-to-peak). The bandwidth of the signal ranges from 0.05 to 100 Hz. To amplify such a small signal, an amplifier with a gain of around 1000 should be applied. AC interference from the power grid should be canceled out along with DC offsets from the electrodes. As a rule, an instrumentation amplifier with a large common-mode voltage suppression is used. The common mode voltage is then amplified, inverted, and fed into a leg electrode for active interference suppression. Additionally, a low-pass filter, a high-pass filter, and a band suppression filter are applied after amplification.All electrical connections of the amplifier must be isolated from mains and from devices supplied from it. It is difficult to construct a power supply with a small amount of stray capacitance to mains. This article presents a battery-powered device that provides a simple solution for a low-cost and isolated power source with a minimum amount of stray capacitance.

Fig. 1 - Structure of ECG analog front-end.
Fig. 2 - Typical ECG of healthy heart.
Fig. 3 - Design configuration of SLG47004.

It details the integration of SLG47004, a fully programmable advanced analog system IC. The SLG47004 AnalogPAK can deliver only one instrumentation amplifier, so this example uses AC filtering on the digital side. A simple DC reference point is used for a leg electrode without active interference cancelation.

A simplified structural scheme of the top of the analog front-end is shown in Figure 1. A typical electric signal from a heart, picked up by the electrodes on the arms, is shown in Figure 2. The typical ECG waveform has five peaks called P-Q-R-S-T. These peaks correspond to the activity of different parts of the heart. The proposed design configuration is shown in Figure 3. It was created in the GreenPAK™ designer software. The complete design file can be found on the Dialog Semiconductor website. 1

Electrical Schematic and Configurations

Fig. 4 - Electrical schematic of analog front-end.

The electrical schematic of the analog front-end is shown in Figure 4. OpAmp0 and 1 use the same configuration, shown in Figure 5. The internal OpAmp configuration is shown in Figure 6, and the HD buffer shares the voltage reference with OpAmp0. In the current project, the internal V ref is disconnected from OpAmp0. The HD buffer and OpAmp0 Vref configurations are shown in Figure 7.

Fig. 5 - Operational amplifier 0 and 1 settings.
Fig. 6 - Internal OpAmp settings.

The rheostat in this project is configured as a digital potentiometer. Its configuration is shown in Figure 8. The configurations of oscillators 0 and 1 are shown in Figure 9. The I2C macrocell uses default configurations, and the general-purpose input/output (GPIO) pins 17, 18, 19, 10, and 11 have the default configuration. The remaining GPIO configurations are shown in Figure 10.

Normal Operation Mode

Power-up pin 15 has a 100 kΩ pull-up resistor, and if left floating, it will by default power up the oscillator, all three op amps, and the rheostat. When pin 15 is pulled down by external components, all internal blocks shut off, and the SLG47004 goes into power-saving mode.

Electrodes on the skin and body have a very high impedance, so common-mode AC power interference is accepted by the electrodes. Instrumentation amplifiers are good at rejecting common-mode signals, and they also have high-impedance inputs, which are needed for amplification of the very small signal produced by heart muscles in a noisy environment.

Fig. 7 - HD buffer and OpAmp0 Vref settings.
Fig. 8 - Digital rheostat 0 and 1 settings.
Fig. 9 - Oscillator 0 and 1 settings.

AC signals from arm electrodes go to an RC high-pass filter (R3, R4, C3, and C4 in Figure 4) with a low cutoff frequency, which eliminates a DC offset that might be present at the input due to the electrochemical processes between the electrode, conductive paste, and the patient’s skin.

An even DC bias of VDD/2 is introduced to both of the op amp inputs to shift the operation point of the op amp, preventing it from going beyond rails. The voltage divider from R6, R7, and R5 (see Figure 4) forms an external negative feedback loop for an instrumentation amplifier from three op amps in the SLG47004 and has a gain of 910.

The internal op amp has four resistors with the same value, forming a differential amplifier with a gain of 1. Op amps have an input offset voltage. In this case, the SLG47004 has a max 1000 μV input offset voltage. This will be amplified by a factor of 910 and can produce up to 1 V of output voltage offset and reduce headroom for the signal, clipping it to GND or VCC (keep in mind that VCC is only 5 V).

To compensate for that error, an auto-trim circuit with a digital potentiometer is used. This uses an analog comparator to switch the direction of the digital potentiometer change (up/down), which is clocked by the oscillator.

This example uses slow tuning of the instrumentation amplifier reference point to cancel out op amp offset voltages. Multiplied by a large gain factor, these voltages will overload the amplifier output without compensation. A slow floating offset voltage presented by muscle shaking, somatic tremor, or galvanic contact of electrode metals to the skin are all sources of interference that must be canceled out. The entire circuit of the comparator, reference voltage, potentiometers, and a clock signal slowly adjust an average DC level of the amplifier to a reference voltage level, which is set to VDD/2. The rate at which the voltage at the potentiometer output is changing is proportional to a clock frequency, fed into a potentiometer block. Assuming the potentiometer has 1023 steps, is connected to a supply voltage of 5 V, and has a clock of 170 Hz, the auto-trim control loop will have a slew rate of 0.83 V/s. It will also act as a high-pass filter with a very low-frequency cutoff.

It is important to consider the error presented by the constant auto-trim process, but in most use cases, this is negligible and can be tolerated. If it is undesirable, it can be configured to be switched off after a trimming period using the internal SLG47004 logic. A reference point of VDD/2 potential is fed into the leg electrode, which also becomes present at both sides of capacitors C3 and C4, preventing them from charging (so you don’t have to wait until the output signal settles due to the input capacitors’ charging time).

Fig. 10 - GPIO settings.

Prototype Testing

Fig. 11 - Seven second heart waveform (500 mV/div, 500 ms/div).
Fig. 12 - Zoomed heart waveform (100 mV/div, 500 ms/div).

Figures 11 and 12 show the waveform at the analog output of the SLG47004. 5 The raw analog output signal has a high level (50 Hz) of noise. Such measurements can’t be analyzed, and this is a typical problem for electrocardiography. For this reason, additional filtering should be applied to the signal.

The common approach is to apply digital filters to remove power grid noise as well as other noise components 2. 2 Many articles describe and compare different digital filtering approaches. 2, 3 Since the purpose of this discussion is to show the performance of the analog front-end, this article skips the digital filter synthesis procedure and shows the filtered signal. Figure 13 depicts the raw digitized signal. At the first filtering stage, 50 Hz noise was removed (see Figure 14). At the second filtering stage, a median filter was applied to the signal (see Figure 15). 6, 7

Fig. 13 - Raw digitized signal.
Fig. 14 - Signal without 50 Hz noise.
Fig. 15 - Signal after median filter.


The SLG47004 can be used as a cost-effective integrated solution for the analog front-end of an ECG monitor. Its unique auto-trim feature allows it to cancel system offset as well as provide steady output. The embedded instrumentation amplifier provides a good common-mode interference rejection, the magnitude of which is much bigger than the signal itself.


  1. GreenPAK Designer Software, Software Download and User Guide, Dialog Semiconductor
  2. AN-CM-326 Analog Front-End for Electrocardiogram Monitor.gp, GreenPAK Design File, Dialog Semiconductor
  3. GreenPAK Development Tools, GreenPAK Development Tools Webpage, Dialog Semiconductor
  4. GreenPAK Application Notes, GreenPAK Application Notes Webpage, Dialog Semiconductor
  5. SLG47004, Datasheet, Dialog Semiconductor
  6. Ondracek O., Jozef P., Elena C., Filters for ECG Digital Signal Processing, International Conference: Trends in Biomedical Engineering, University of Zilina, September 7–9, 2005, p. 91–96.
  7. Hosseini H., Nazeran H., Reynolds K., ECG Noise Cancellation Using Digital Filters, 2nd International Conference on Bioelectromagnetism, 1998, p. 151– 152.

This article was written by Svyatoslav Skalskyy, Product Development Engineer, Dialog Semiconductor, A Renesas Company, Lviv, Ukraine. For more information, visit here .